Chip Name: FPMA-2

Chip Function: Field-Programmable Analog Array for reconfigurable sensor electronics (Miller, Cascode, Instrumentation Amps.) with advanced matching features in intrinsic evolution approach.

Technology: 0.35um CMOS Austriasmicrosystems

Chip data: 4.75 mm2

Designer: S.K. Lakshmanan

Year: 2007, Funding: Phytec

Chip Name: LOC

Chip Function: Vision chip implementing Local-Orientation-Coding for orientation extraction and texture analysis. Digital output of winning kernel ID.

Technology: 0.6um CUQ CMOS Austriasmicrosystems

Chip data: 16x26 pixels, decoders, 10ms/256 kernels, 130um x 100 um pixel area, 2600um x 3400um chip area

Designer: J. Skribanowitz, C. Mayr et al.

Year: 2002, Funding: DFG, SPP VIVA

Chip Name: Reconfigurable Classifier

Chip Function: Low-power analog reconfigurable classifier chip employing 1-nearest-neighbor concepts. Developed as case-study of holistic low-power recognition system design.

Technology: 0.6um CUQ CMOS Austriasmicrosystems

Chip data: 8x8 classifier field, 6-bit RAMDACs, area

Designer: J. Döge

Year: 2002, Funding: DFG, SPP VIVA

Chip Name: ELAC

Chip Function: Vision chip implementing Extended-Local-Auto-Correlation for orientation extraction and texture analysis. Digital output of winning kernel ID.

Technology: 0.6um CUQ CMOS Austriasmicrosystems

Chip data: 16x16 pixels, decoders, 10ms/20 kernels, 220um x 200um pixel area, 4200um x 3962 um chip area

Designer: J. Skribanowitz, C. Mayr et al.

Year: 2002, Funding: DFG, SPP VIVA

Chip Name: Eletronic Fovea

Chip Function: Vision chip implementing an eletronically programmable foveating mechanism by anisotropic smoothing and non-equidistant pixel read-out.

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: x pixels, decoders, pixel area, chip area

Designer: J. Skribanowitz

Year: 2000, Funding: DFG, GK Sensorik

Chip Name: LuCoS 1k128/1M128

Chip Function: Spiking row imager chip transducing incident light flux into spike rate. Rates accumulated in counters, digital output signal (auxiliar analog spiking output). See project page !

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: 128 pixels, asynchronous 16/20 bit counters, decoders, pixel area, chip area

Designer: J. Döge

Year: 1999, Funding: SARAD GmbH

Chip Name: LAPIS

Chip Function: Vision chip implementing an local-adaptive pixel cells for improved HDR image acquisition.

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: 96 x 32pixels, decoders, fill-factor 3.5%, 22.2 mm2 chip area

Designer: J. Skribanowitz

Year: 1999, Funding: DFG, GK Sensorik

Chip Name: DoG-Sensor

Chip Function: Vision chip implementing spatio-temporal smoothing and contour extraction (DoG) for in-line inspection.

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: x 3 pixels, decoders, chip area

Designer: J. Skribanowitz

Year: 1998, Funding: DFG, GK Sensorik

Chip Name: OCR_Metering-Sensor

Chip Function: CMOS Image sensor (APS) for OCR in remote meter reading, designed under cost constraints (See project page !)

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: 180 x 27 pixels, 6-bit ADC, fill-factor 22.5 %, 24k trans., 32um x 32um pixel area, 9.75 mm2 chip area

Designer: S. Getzlaff

Year:1998, Funding: Phytec

Chip Name: MPC 98

Chip Function: Collection of operational amplifiers designed as semester projects by students of design course

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: 6 amplifiers, 5 mm2

Designer: SS 98 students & A. König

Year:1998, Funding: self-funded

Chip Name: MPC 99

Chip Function: Programmable filter in SC-technology. Designed as semester group project by students of design course in the context of a PhD project.

Technology: 0.8um CYE CMOS Austriasmicrosystems

Chip data: 6 amplifiers, 5 mm2

Designer: SS 99 students & T. Ferchland

Year:1999, Funding: self-funded

Chip Name: ARAMYS II

Chip Function: Flexible neural associative memory chip for scaleable network, implementing AND, Hamming, and City-Block metrics and fast parallel WTA. 32 neurons per chip

Technology: 1.0um CMOS ES2

Chip data: 32 neurons, 8/16 bit resolution, 56 mm2, 133.8 k trans., 23 Mhz

Designer: M. Gumm

Year:1993, Funding: self-funded

System Name: ARAMYS II System

System Function: Prototype of neural associative memory system based on 4 ARAMYS II chips. Application to vector quantization, SOM, and classification by RCE, LVQ, or kNN.

System data: 128 neurons, 8/16 bit resolution, TMS 320C25 controller, PC-host, C-application.

Year:1993/94, Funding: self-funded

System Name: BACCHUS I System

System Function: Prototype of neural associative memory system based on 16 BACCHUS I chips. Tentative application to vector quantization, SOM, and classification by LVQ, or kNN employing thermometer coding.

System data: 512 neurons, 1/8 bit resolution, random logic controller, PC-host, max. 512 GCPS@10 Mhz, C-application.

Demo-Video by M. Pöpel

Year: 1991 , Funding: self-funded