6th International Conference on Microelectronics
for Neural Networks, Evolutionary & Fuzzy Systems

Overview of MicroNeuro'97:

• Conference Scope and Topics
• Chair Persons
• Steering Committee
• International Program Committee
• Organizing Committee
• Conference Schedule
• Submission Information
• Registration Information
• Presenters Information
• Conference Programme
• Conference Location
• Travel Information
• Dresden and Surroundings

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Doz. Dr. A. König
Chair of Electron Devices and Integrated Circuits
Faculty of Electrical Engineering
University of Technology Dresden
D-01062 Dresden
Tel. +49 351 463 2805
Fax. +49 351 463 7260
koenig@iee.et.tu-dresden.de

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Submission of Papers                         May  31, 1997
Notification of Acceptance                   July 11, 1997
Submission of Final Camera-Ready Paper       Aug.  8, 1997
Early Registration                           July 15, 1997
Main Conference                              September 24-26, 1997 

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Five copies of a manuscript typed on A4 (US) paper, 2 columns, 10pt or larger, maximum 8 pages including figures plus a cover page indicating title, authors name, affiliation, address, phone no. should be sent to the MICRONEURO'97 conference secretariat. The authors should indicate which category describes the topic of the paper best.
The choice of a local publisher allows a relaxed conference schedule. The final deadline for submission is May 31, 1997. Notification of acceptance is due at July 11, 1997. Proposed contributions will be evaluated by an international program committee. Papers published elsewhere will be returned without review. A proceedings volume will be provided at the conference, and publication of selected papers by an international publisher is intended.
The final camera ready version should adhere to the author guidelines given here.
A LaTeX style file and a sample tex file for paper compilation is given here.
Additionally, a format file for FrameMaker is provided here.
With other text processors, please follow the given author guidelines as close as possible.

Printing of an accepted paper in the proceedings requires the registration of at least one author and the return of the filled and signed Authors Submission and Copyright Transfer Form .

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Registration forms and information will be sent to you on request to MICRONEURO'97 Conference Secretariat (E-Mail: mneuro97@iee.et.tu-dresden.de), or can be obtained here (MS-Word prn-file).

E-Mail registrations cannot be accepted, because signatures are needed on file.

 
Registration fee         before July 15, 1997          after July 15, 1997

Delegate                        DM 420,-                    DM 450,-
Students                        DM 300,-                    DM 300,-
TUD Members/Students*           DM  50,-                    DM  50,-
Banquet Tickets                 DM  80,-                    DM  80,-
Lunch Tickets (per day)         DM  18,-                    DM  18,-

*The registration fee for TUD members and TUD students does not include the proceedings. Proceedings can optionally be purchased at the conference desk.

Payment:

in Deutsche Mark only, covering registration fee and all bank charges and fees, may be made in two ways:

 - either by cheque mailed with the registration form and payable to the
   order of MicroNeuro'97 - Dresden, Germany
 - or by bank transfer or money order sent to MicroNeuro'97, 
   Code:            707
   Account No.:     353 861 968
   Bankleitzahl:    850 551 42
   Stadtsparkasse Dresden

Cancellation:

Cancellation is free of charge until July 15, 1997. After July 15, the registration fee minus 20% will be refunded, if cancellation is received before August 31, 1997. From September 1, 1997 no refunding is possible.

Hotel Accomodation:

The following hotels offer rooms (bed and breakfast) at reduced rate for the duration of the conference (September 23 - 27, 1997):

IBIS-Hotel ''Bastei''         Single Room            DM 144,- 
Prager Strasse                Double Room            DM 159,- 

Hotel Mercure NEWA            Single Room            DM 188,- 
St. Petersburger Str.         Double Room            DM 218,- 
 
Hotel Ramada                  Single Room            DM 149,- 
Melanchthonstr.2              Double Room            DM 193,-
 

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Proposals for presentation at the exhibition are welcome. Please contact the Organizing Committee. Participation at the exhibition is free of charge. In addition, one person per presentation can participate without charge at the scientific part of the conference. The final Conference Programme can be obtained here.

Programme at a Glance:

Wednesday, Sept. 24: 
           
 8.00  Tutorial -- Prof. Yamakawa, Kyushu Inst. of Techn., Japan                        

12.00  Lunchbreak

14.00  Conference Opening by Prof. U.Ramacher

14.10  Session 1 - VLSI Systems and their Application 
       Chairman: U. Ramacher, München              
       Invited Talk -- Dr. Kyuma, Mitsubishi, Japan
       Oral Presentations  
           
16.50  Coffee break and Visit of the Exhibition

17.10  Session 2 - VLSI Adequate Design of Neural Systems
       Chairman: S.R. Jones, Loughborough

18.30  Welcome Reception

Thursday,  Sept. 25:   
      
 
 8.00  Session 3 - Bio-Inspiration I
       Chairman: E.Vittoz, Neuchatel
       Invited Talk - Dr. Goebel, MPI, D-Frankfurt
       Oral Presentations   
          
10.15  Coffee break and Visit of the Exhibition

10.35  Session 4 - Neuro-Fuzzy Circuits and Systems
       Chairman: U.Rückert, Paderborn
       Invited Talk -- Prof. Yamakawa, Kyushu Inst. of Techn., Japan
       Oral Presentations             

12.10  Lunchbreak

13.30  Postersession I and Visit of the Exhibition

14.30  Session 5 -  Bio-Inspiration II
       Chairman: A.Prieto, Granada
       Invited Talk -- Prof. Hartmann, Univ. GH Paderborn, D-Paderborn                               
       Oral Presentations                                                             

17.10  Coffee break and Visit of the Exhibition

19.00  Guided tour to the historical city center of Dresden

20.00  Conference Banquet at ''Italienisches Dörfchen'' and ensuing concert 

Friday, Sept. 26:  
         

 8.30  Session 6 - Analog VLSI Circuits and Systems I
       Chairman: T. Yamakawa, Fukuoka
       Invited Talk -- Prof. Vittoz, CSEM, CH-Neuchatel
       Oral Presentations   

10.20  Coffee break and Visit of the Exhibition          

10.40  Session 7 - Analog VLSI Circuits and Systems II
       Chairman: T.Shibata, Tokyo
       Oral Presentations 
 
11.55  Lunchbreak

13.30  Postersession II and Visit of the Exhibition

14.30  Session 8 - Intelligent Robots, Neural Sensors,
                   Potential Technologies
       Chairman: K. Goser, Dortmund
       Invited Talk -- Prof. Buhmann, Univ. Bonn, D-Bonn
       Oral Presentations    
         
16.45  Closing of the Conference by Prof. U.Ramacher  
17.00  End of the Conference

Invited Talks:

Dr. Kazuo Kyuma , Mitsubishi Electric Corp., Japan,
Email: kyuma@qua.crl.melco.co.jp
''Concept, Design, Performance and Applications of Artificial Retina Chips''

Digital neurochips and artificial retina chips developed in Mitsubishi Electric Corp. will be introduced. Their configurations, performance, and typical applications are described. We are going to focus our talk on the application of artificial retina chips to the interactive games based on the gesture recognition.

Dr. Rainer Goebel , Max-Planck-Institut für Hirnforschung, Frankfurt/Main, Germany, Email: goebel@mpih-frankfurt.mpg.de
''Biology inspired neuron models and networks: the functional role of temporal coding''

After a brief discussion of the range from very simple to rather complex neuron models, networks of units with oscillatory and bursting properties are presented. It is shown that these networks may produce stimulus-dependent synchronization of neuronal responses on a time scale of milliseconds in good agreement with recent neurophysiological findings. These networks successfully solve the binding problem since assemblies of cells are distinguished by the temporal coherence of the responses of the constituting neuron models. As an application of this type of network a large-scale model of visual scene perception is presented which possesses mechanisms for perceptual organisation, visual selective attention and invariant shape recognition. A simpler version of this model was recently embedded in a mobile robot.

Prof. Joachim M. Buhmann , Informatik III, University of Bonn, Germany,
Email: jb@uran.informatik.uni-bonn.de
''How RHINO gets around in the world ? Hardware and software challenges for autonomous robots''

The autonomous robot RHINO of the University of Bonn can orient itself in an office environment, it can detect and pick up objects, it can guide visitors in the technical exhibition of the ``Deutsches Museum'' and is serves as an extraordinary challenging testbed/platform for advanced research on adaptive systems. This talk will survey the presently implemented capabilities of RHINO and its limitations. Emphasis will be put on potential hardware solutions for vision and signal processing to alleviate the realtime processing constraint which are indispensible for boosting RHINO's adaptivity and its capability to act in variable and densely populated environments.

Prof. Eric Vittoz , CSEM, Neuchatel, Switzerland, Email: eric.vittoz@csemne.ch
''Pseudo-resistive networks and their applications to analog collective computation''

The basic concept of using a standard MOS transistor as pseudo-conductance will be explained. Its potential for implementing new architectures for collective signal processing will be discussed and illustrated by several practical examples.

Prof. Georg Hartmann , Heinz-Nixdorf-Institut, University of Paderborn, Germany, Email: hartmann@get.uni-paderborn.de
''SPIKE128K - an accelerator for dynamic simulation of large pulse coded networks''

Labelling of features by synchronization of spikes seems to be a very efficient encoding scheme at least in the visual system. Simulation of a vision system with millions of pulse-coded model neurons, however, is almost impossible on the basis of available processors including parallel processors and neurocomputers. A "one to one" silicon implementation of the pulse-coded model neurons suffers from communication problems, and low flexibility. On the other hand, acceleration of the simulation algorithm of pulse-coded leaky integrator neurons proved to be straightforward, flexible, and very efficient. We developed an accelerator for a special version of the French and Stein neurons with modulatory inputs which are advantageous for simulation of synchronization mechanisms. Up to 128K neurons with a total number of 16 M freely allocatable synapses are simulated within one system. The size of networks, however, is not at all limited by these numbers, as the system may be arbitrarily expanded. Simulation speed obviously depends on the number of interconnections, and on the average activity within the network. In the case of locally interconnected networks for simulation of vision mechanisms there is only a very low percentage of simultaneously active neurons. In these cases our accelerator provides close to real-time behaviour if one second of a biological neuron is simulated by 1000 time slots. The prototype of the SPIKE128K accelerator is demonstrated at the exhibition.

Prof. Takeshi Yamakawa , Kyushu Institute of Technology, Iizuka, Fukuoka 820, Japan, Email: yamakawa@ces.kyutech.ac.jp
''Similarities and Differences between Fuzzy Systems and Other Soft Computing Tools''

This paper describes what is a fuzzy inference and how it can be implemented in silicon from a tutorial viewpoint. The fuzzy inference with defuzzification exhibits good designability, good generalization of a complicated system and easy adaptation to the change of the system. The similarities and the differences among fuzzy IF-THEN rules, mathematical equations, crisp IF-THEN rules, artificial neural networks, RBF networks, wavelet networks. Fusion technology between fuzzy systems and other soft computing tools and future trends of hardware implementations are touched upon.

Keywords : Soft computing, fuzzy inference with defuzzification, IF-THEN rules, description of nonlinear systems, neuroscience, RBF network, wavelet network.

Prof Takeshi Yamakawa , Kyushu Institute of Technology, Iizuka, Fukuoka 820, Japan, Email: yamakawa@ces.kyutech.ac.jp
''Basic Aspect of a Fuzzy System and Its Hardware Implementation in Analog Mode''

Abstract:
This tutorial lecture is dedicated to the people who are not familiar to fuzzy logic and its applications, but familiar to electronic circuits and devices. After this tutorial lecture, the audience will become to be interested in fuzzy systems and attracted to design fuzzy electronic circuits.
Contents:

1. What is a Fuzzy System?
   1.1 Description of a nonlinear system
   1.2 Fuzzy sets (Fuzzy linguistic information)
   1.3 Difference between fussiness and randomness
        
2. Fuzzy Inference.
   2.1 Mechanism of fuzzy inference
   2.2 Interpolation characteristics of several types of inferences.
   2.3 Weighting of antecedent variables
   2.4 Weighting of consequent variable (rule)

3. Why is a Fuzzy Hardware Necessary?
   3.1 Processing Speed
   3.2 Processing cost
     
4. Overview of Fuzzy Hardware Systems. (Digital and Analog)
   4.1 Differences between a traditional analog circuit and a fuzzy 
       circuit in analog mode
   4.2 Differences between digital and analog fuzzy systems
               (speed, chip area, programmability, compatibility with 
                sensors and processors, design tools)

5. History of Fuzzy Hardware Systems in Analog Mode.
   5.1 Current mode and voltage mode
   5.2 Min & Max circuits in current mode
   5.3 Membership function circuit in current mode
   5.4 Min & Max circuits in voltage  mode
   5.5 Membership function circuit in voltage mode
   5.6 Grade-controllable membership function circuit in voltage 
       mode
          (suitable for weighting in antecedents and for defuzzification
            without division operation)
   5.7 Membership Function Circuit in Current Mode             
   5.8 Membership Function Generator                                   
   5.9 Fuzzy inference engine in voltage mode
   5.10 Defuzzifier in voltage mode
   5.11 Defuzzification without division operation
        
6. Fuzzy Logic Controller. 
   6.1 Architecture of a fuzzy logic controller
   6.2 How to design a fuzzy logic controller         
   6.3 Wine glass stabilization (Mouse stabilization)         

7. Future Trends of Fuzzy Hardware systems.

Dupal Bernd, Sagerl Martina,
Institut für Gestaltungs- und Wirkungsforschung, TU Wien, Austria
''Darwin98 - Dynamisches ARtifizielles Wiener ImpulsneuronenNetz''

The presented program package simulates networks of spiking neurons for the research of excitation and learning processes. The program runs on a common pentium PC with 16 MB of RAM under MS-DOS 5.0 (or higher) with SVGA-compatible graphics adapter. It contains many tools for the creation and modification of such networks with utilities for logging and evaluation of the generated results. A large amount of parameters can be adjusted to provide the ability of a very flexible experimentation. The focus has been laid on a powerful user-friendly graphical environment. Currently, the program can maintain online any free-structured network of several hundred neurons.

S. Neußer, B. Friebe, Institute of Microelectronics Stuttgart (IMS), Germany
SAND Neural Processor and PCI Neuroboard

SAND (Simply-Applicable Neural Device) is a neural processor based upon the principle of a systolic array. Four parallel processor elements form the heart of this array. Each processor element has a multiplier and two adders. With these elements the scalar product and the vector distance can be calculated. A post-processing module allows the determination of the largest and smallest output activity. The following types and sizes of neural networks are supported by SAND:

• multilayer perceptrons (MLP), 512-64-64-64-64 (I-H-H-H-O)
• radial basis function networks (RBF), 512-64-64-64-64 (I-H-H-H-O)
• Kohonen Feature maps, 512-256 (I-O)

Very few external peripheral components are necessary for the operation of SAND. A weight store RAM, a look-up table RAM for the non-linear transfer function, and a FIFO for temporary data storage are needed. The memory management and the control of the SAND is being performed by a sequencer component (FPGA), which provides a simple macro command set.

With a maximum clock frequency of fmax = 50 MHz SAND achieves a performance of 200 MCPS. Multiple SAND chips may be connected in parallel in order to obtain a further increase in performance. SAND has been designed in a co-operation between the IMS and the Forschungszentrum Karlsruhe.

The PCI neuroboard contains up to four SAND chips. Therefore the overall peak performance increases to 800 MCPS. The board uses a standard PCI-Interface and can excellently be used to accelerate network types mentioned above. The PCI board has been designed by the Forschungszentrum Karlsruhe and the distributor INCO Systeme GmbH. Neural simulators for UNIX operation systems and Windows 95/NT are available as well as low level C interfaces.

S. Neußer, B. Friebe, Institute of Microelectronics Stuttgart (IMS), Germany
SIOP2 Neurochip and SCSI Neuroboard

The neurochip SIOP2 (Serial Input Output Parallel device) is an universal neural controller for high data processing rates. On the chip a feedforward network with RAM weights and a quadratic transfer function has been implemented in fully parallel hardware. With the internal layout elements synapse, dendrite and neuron various network topologies with up to two hidden layers can be configured. Due to the flexible architecture several neurochips can be cascaded together to form more complex neural controllers. SIOP2 achieves a performance of 350 MCPS with a maximum clock frequency of fmax = 50 MHz.

For prototyping purposes in scientific and industrial environments a neuroboard with three SIOP2 chips has been designed in a co-operation between the IMS Stuttgart and the GEMAC Chemnitz. Several feedforward network topologies can be reconfigured on the board with an achievable performance of more than 1 GCPS. The board provides a robust and fast SCSI-2 interface, a serial V.24 interface, 16 A/D- and 8 D/A-converter channels. An automatic weight and configuration initialisation is being executed in case of a reset or power-on. Together with the analog interface a standalone system operation is supported. The following list gives the maximum configurations available on the neuroboard:

• 10 x 40 x 5 x 9
• 20 x 20 x 10 x 9
• 40 x 10 x 10 x 9
• 40 x 15 x 9

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• Landeshauptstadt Dresden/ Saxon Capital Dresden
• Stadtinformationen/City Information
• Online Information-System of Dresden
• Stadtansichten/City Views
• Sächsische Schweiz/Saxonian Switzerland

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Doz. Dr. A. König , Dr. S. Schmidt, J. Wieczorek, and KSTU Dresden GmbH

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