Zur Hauptnavigation / To main navigation

Zur Sekundärnavigation / To secondary navigation

Zum Inhalt dieser Seite / To the content of this page

Sekundärnavigation / Secondary navigation

Inhaltsbereich / Content

EIT-EIS-560-V-4 (with class project: EIT-EIS-562-M-7)

Verification of Digital Systems

Tuesday
Thursday
13:45 - 15:15
13:45 - 15:15
Room: 11-241
Room: 11-243

2 hours of lecture / 2 hours of assignments (5 ECTS credits) plus 3 ECTS class project (optional)

Start: Thursday, October 26, 2017

Content

Ensuring functional corectness of a complex System-on-Chip consumes 60-80% of the total design costs. This lecture presents basic principles of formal verification techniques and their application within state-of-the-art design flows. 

  • Graph Representations of Boolean Functions
  • Formal Property Checking an Overview
  • Model checking with Temporal Logic
  • Symbolic Traversal of Finite State Machines
  • SAT-based Property Checking
  • Equivalence Checking

 

Exercise

see extra webpage

 

Adding the Class Project: EIT-EIS-562-M-7

A class project is offered to students with expertise in C++ programming. An additional 3 ECTS (2SWS) can be earned when participating in the class project, see extra webpage.

 

 

Literature

Gary Hachtel, Fabio Somenzi: Logic Synthesis and Verification Algorithms, Springer, 2010, EIT 864/089, L INF 38

 

 

Downloads

For download material and further information please use OpenOLAT.
(Access information for the course is given in class.)


Exam dates

to be announced