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This course is taught in English.
Modern technology relies more and more on computing systems, impacting all aspects of human life. The complexity of these systems is constantly growing and so is their vulnerability against design errors, manufacturing defects and faults occurring during operation. Additional challenges result from latest manufacturing technologies which are inherently more susceptible to process variations, leading to unreliable circuit devices. This lecture discusses techniques to make digital systems robust against such faults and errors.
- Metrics of fault tolerance (reliability, availability, failure rate, MTTF, Weibull distribution, system reliability analysis)
- Structural Redundancy (triple-modular redundancy, N-modular redundancy, dynamic redundancy, hybrid schemes)
- Information Redundancy (codes and their properties, error detection and correction, parity codes, Hamming code, Hsiao code, checksum codes, cyclic codes, AN codes, residue codes)
- CMOS Failures(overview of failure causes in CMOS circuits: manufacturing defects, process variations, aging effects, soft errors)
- Fault Models (abstraction levels of fault models, transistor-level fault models, gate-level models, stuck-at faults, delay faults, bridging faults)
- Fault Simulation and Test Generation (fault simulation applications and algorithms, random test generation, structural ATPG, SAT-based ATPG, sequential test generation)
- Design for Testability (scan design, Built-in self test (BIST), offline BIST, online BIST)
- Hardware Redundancy Techniques (circuit-level resilience techniques (BISER, Razor), concurrent error detection, self-checking circuits)
- Software-based Resilience (checkpointing & recovery, software-based concurrent error detection)