Embedded Systems Laboratory (Labor Digitaltechnik II)
|Wednesday||14:00 - 17:00||Room: 12-524|
4 hours of laboratory (5 ECTS credits)
Start: Wed, 2018-04-11,
Introductory meeting: 14:00-15:00, Room: 13-222.
Attendance is required to claim seat.
Registration is mandatory for this lab.
Seats are assigned on a first-come first-serve basis.
This laboratory course is offered in both, winter and summer semesters.
Winter: Tuesdays, 14:00-17:00h, Room 12-524
Summer: Wednesday, 14:00-17:00h, Room 12-524
Registration is mandatory!
Please note: The number of available seats for this lab is limited. In order to participate you need to follow these steps:
- Make sure you have a valid university email address (email@example.com). Set your KIS account to use this email address.
- Register succesfully for a seat using the KIS system through your KIS account. (For information on the course, see the KIS page for this course.) You need to find the course in the current semester directory and then click on the link for registration ("Zum Anmeldeverfahren").
- Claim your seat at the introductory meeting. If you do not show up your seat will be given to somebody from the waiting list.
The number of seats cannot be extended.
If no more seats are available when you try to register, the registration system will put you on a waiting list. During the registration period you will be registered automatically once a seat becomes free. If you are still on the waiting list at the time of the introductory meeting there is a small chance that you can move in for somebody not claiming their seat.
Otherwise: The lab is offered also in the next semester.
Downloadable material is provided using OpenOLAT. Access information for the course is given in class.
Link to the course:
Design, Implementation, Synthesis and Test of Embedded Systems
The goal of this laboratory course is to gain an understanding of the general design methodology of communicating embedded systems as they are employed in technical systems in various fields, such as automotive systems, production automation and control, and mobile communication.
Dipl.-Ing. Thomas Fehmel
You should bring sufficient knowledge from these fields:
- Digital systems architectures, as taught in the courses Architecture of Digital Systems 1 and Architecture of Digital Systems 2
- Assembler programming (see Chair of Real-Time Systems)
- Digital design at the RTL, using a high-level description language (VHDL)
☞ Please note: This is an advanced course. The objective of this course is to understand the interaction of hardware and software at the machine and RTL level. The objective is not to teach you fundamentals of software programming or digital design using VHDL. If you lack skills in programming or VHDL design then this lab will require significant extra effort.
In the beginning of the semester (date, time and location will be posted on this page) there will be an introductory meeting where you will be given all the details concerning the organisation of the lab course.
The lab is a project lab course. You will be working in a small team. During the first few weeks of the semester your team will complete a number of pre-defined tasks of developing hardware and software on the target platform. The goal of this "warm-up phase" is to make you familiar with the development platform and environment.
During the remaining time you as a team will be designing, implementing and testing an (embedded) computing system. You are responsible for the concept, architecture design, implementation and verification of the hardware and software of this project. You as a team will have to present a project plan which will be discussed in a short review meeting.
Lab support and evaluation will be given during the lab hours (see above). In the remaining time you may work either in the laboratory (Room 524), provided there is space, or at home.
Your successful completion of the lab course will be communicated to the university's examination office ("Abteilung für Prüfungsangelegenheit") if all tasks of the project have been completed and the solutions have been presented.