Synthesis and Optimization of Microelectronic Systems II
|08:15 - 09:45|
15:30 - 17:00
Prof. Ciesielski is available for office hours
on Wednesdays at 15:30 in room 12-528
The course is dedicated to Master's students of electrical and computer engineering with specialization in Embeddeded Systems or Integrated Systems. 3 ECTS credit points can be earned. An exam will be offered during the last week of the lecture period (July 10 - 14).
This lecture is part of the Erasmus Mundus Distinguished Lecture Series on Embedded Systems and will be given by Prof. Maciej Ciesielski, University of Massachusetts at Amherst, USA.
No previous knowledge is required from "Synthesis and Optimization of Microelectronic Systems I". Part I deals with the higher design levels while part II of the lecture focuses on lower design levels. Both parts can be attended independently from each other.
More information and documentation can be found on the UMass Logic Synthesis course website.
Prof. Maciej Ciesielski, University of Massachusetts at Amherst, USA [E-mail]
Maciej Ciesielski received the M.S. in Electrical Engineering from Warsaw Technical University in 1974, and Ph.D. in Electrical Engineering from the University of Rochester in 1983. From 1983 to 1986 he was a Senior Member of Technical Staff at GTE Laboratories, Waltham, MA, where he worked on silicon compilation and layout synthesis projects. In 1987 he joined the Department of Electrical and Computer Engineering at the University of Massachusetts, Amherst, where he is currently Professor and Associate Department Head. He teaches and conducts research in the area of electronic design automation, and specifically in high-level and logic synthesis, formal verification and design validation of digital systems. He is recipient of Doctorate Honoris Causa from the Université de Bretagne Sud, Lorient, France, in 2008. He is a senior member of the IEEE.
For more details consult his web site.
1.Introduction to logic synthesis
- VLSI design flow
- VLSI technologies (PLAs, standard cells, FPGAs)
2. High level synthesis, basics
- Datapath vs control logic
- scheduling, resoource allocation, binding
3. Boolean functions and their representations
- Sum of products, factored form representations
- Canonical representations, BDDs, BMDs, others
4. Two-level logic optimization
- Exact logic minimization (Quine)
- Heuristic logic optimization (Espresso)
5. Functional decomposition
- Asenhurst-Curtis method
- BDD based decomposition, bi-decomposition
6. Multi-level logic synthesis (technology independent)
- Kernel-based algebraic decomposition (SIS)
- AIG-based optimization (ABC)
7. Technology mapping
- Graph based, standard cell mapping (ASICs)
- Cut-based (FPGAs)
8. Sequential optimization
- Retiming and resynthesis
- Integrating synthesis, retiming and mapping (ABC)
Exam: Written (closed books, closed notes), will be held on July 13, 2017, at 15:30 in the lecture room.
[DeGh94] S. Devadas, A. Ghosh, K. Keutzer:
Logic Synthesis, McGraw-Hill,
1994, ISBN 0-07-016500-9.
[DeMi94] G. De Micheli: Synthesis and Optimization of Digital Circuits,
McGraw-Hill, 1994, ISBN 0-07-016333-2.
[HaSo96] G. Hachtel, F. Somenzi:
Logic Synthesis and Verification Algorithms,
Kluwer Academic Pulischers, 1996, ISBN 0-7923-9746-0.
[HaSa02] S. Hassoun, T. Sasao: Logic Synthesis and Verification,
Kluwer Academic Publishers, 2002, ISBN 0-7923-7606-4.
A complete text of textbook "Synthesis and Optimization of Digital Circuits" by Giovanni deMicheli is available HERE
Retiming is covered on pages 462-471 (book) or 471-480 (pdf file) but it basically covers the entire course (and more!).
You can also see the paper by Shenoy and Rudell, "Efficient Implementation of Retiming", 1994:
You only need to read first three pages (up to Section 3.2) to get a good idea about retiming.
( will be updated during the semester )
Access information for the course material is given in the lecture.
|1. Introduction to logic synthesis||SMSII-intro.pdf|
|2. High level synthesis basics ||HLS-scheduling.pdf|
|3. Logic synthesis basics||Logic-synthesis2-basics.pdf|
|4. Exact 2-level logic optimization||Logic-synthesis3a-Quine.pdf|
|5. Heuristic 2-level logic optimization||Logic-synthesis3b-espresso.pdf|
|6. Binary Decision Diagrams||Logic-synthesis3c-BDD.pdf|
|Assignment 2:||sms2-hm2-2017.pdf |