(with class project: EIT-EIS-562-M-7)
|13:45 - 15:15|
13:45 - 15:15
2 hours of lecture / 2 hours of assignments (5 ECTS credits) plus 3 ECTS class project (optional)
Start: Tuesday, October 29, 2019
- Changes to lecture and exercise times are regularly published on the OpenOLAT web page of this course.
Ensuring functional corectness of a complex System-on-Chip consumes 60-80% of the total design costs. This lecture presents basic principles of formal verification techniques and their application within state-of-the-art design flows. These techniques also set the frame for new, evolving approaches to safety and security analysis in embedded systems (research projects possible).
- Graph Representations of Boolean Functions
- Formal Property Checking an Overview
- Model checking with Temporal Logic
- Symbolic Traversal of Finite State Machines
- SAT-based Property Checking
- Equivalence Checking
see extra webpage
Adding the Class Project: EIT-EIS-562-M-7
A class project is offered to students with expertise in C++ programming. An additional 3 ECTS (2SWS) can be earned when participating in the class project, see extra webpage.
Gary Hachtel, Fabio Somenzi: Logic Synthesis and Verification Algorithms, Springer, 2010, EIT 864/089, L INF 38