Content

Ensuring functional corectness of a complex System-on-Chip consumes 60-80% of the total design costs. This lecture presents basic principles of formal verification techniques and their application within state-of-the-art design flows.  These techniques also set the frame for new, evolving approaches to safety and security analysis in embedded systems (research projects possible).

• Graph Representations of Boolean Functions
• Formal Property Checking an Overview
• Model checking with Temporal Logic
• Symbolic Traversal of Finite State Machines
• SAT-based Property Checking
• Equivalence Checking
• Laboratory: Introduction into SystemVerilog Assertions (SVA), verification tasks using commercial tool