Verification of Digital Systems
EIT-EIS-560-V-4
Additional class project (optional): EIT-EIS-562-M-7
| Tuesday Thursday | 14:00 - 15:30 14:30 - 16:00 | Room: 11-207 Room: 24-102 |
2 hours of lecture / 2 hours of assignments (5 ECTS credits) plus 3 ECTS class project (optional)
Start: Thursday, October 28, 2021
Examination: Verification of Digital Systems
| Exam Date: | 2022-02-22 2022-04-07 |
| Overflow Date: | 2022-02-21 2022-04-06 |
DOWNLOADS
For download material and further information please use OpenOLAT. (Access information for the course is given in class.)
News
- Changes to lecture and exercise times are regularly published on the OpenOLAT web page of this course.
Content
Ensuring functional corectness of a complex System-on-Chip consumes 60-80% of the total design costs. This lecture presents basic principles of formal verification techniques and their application within state-of-the-art design flows. These techniques also set the frame for new, evolving approaches to safety and security analysis in embedded systems (research projects possible).
- Graph Representations of Boolean Functions
- Formal Property Checking an Overview
- Model checking with Temporal Logic
- Symbolic Traversal of Finite State Machines
- SAT-based Property Checking
- Equivalence Checking
Exercise
see extra webpage
Adding the Class Project: EIT-EIS-562-M-7
A class project is offered to students with expertise in C++ programming. An additional 3 ECTS (2SWS) can be earned when participating in the class project, see extra webpage.
Literature
will be presented in lecture