M.Sc. Paulius Morkūnas
Tel: (+49) (631) 205-2848
I am researching in the field of Electronic System-Level (ESL) design and formal RTL verification. I aim to develop a methodology allowing rapid guided top-down design flow of formally sound pipelined RTL implementations from their ESL counterparts.
Bridging the semantic gap between these two abstraction levels would allow using ESL models as golden the same way the RTL is used now. The flow is based on generating a complete set of properties from an ESL model that serves as guidance and supervision in the designing process of the hardware. Currently, the main focus is to tailor this flow for processor designs.
Key work areas:
Formal verification with OneSpin (ITL, SVA)
Temporal decomposition of existing RISC-V cores (HDL)
ESL modelling (SystemC)
Flow automation (C++, Python)