Fachgebiet Entwurf Informationstechnischer Systeme (EIS)

M.Sc. Lucas Deutschmann

Room: 12/545

Tel: (+49) (631) 205-2685

E-Mail: deutschmann(at)eit.uni-kl.de

GitHub: https://github.com/Seek64

 

Courses & Tasks:

 

Research:

I am currently researching in the field of hardware security with a focus on conventional side channels.
Previous research covered:

  • Generating RTL designs from untimed SystemC models (Operation-Level Synthesis)
  • Fault-Injection based Analysis for identifying Resource sharing Opportunities
  • Exploiting Formal Verification to improve Lockstep Architectures

 

Publications:

  • L. Deutschmann, J. Müller, M. R. Fadiheh, D. Stoffel, and W. Kunz, “Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing,” to be published in IEEE/ACM Design Automation Conference (DAC). IEEE, 2022
  • L. Deutschmann, J. Schauss, T. Ludwig, D. Stoffel, W. Kunz: Operation-Level Synthesis, 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'21), Virtual Event, Germany, March 2021.
  • T. Ludwig, M. Schwarz, J. Urdahl, L. Deutschmann, S. Hetalani, D. Stoffel, W. Kunz: Property-Driven Development of a RISC-V CPU, Design and Verification Conference US (DVCON US), San Jose, CA, Feb. 2019.

 

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