Decompositon in Asynchronous Circuit Design

Examples

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• FIFO-queue controller
• Low latency arbiter
• VME bus controller
• Locked2
• Stg-Blunno

FIFO-queue controller

Specification N (832 reachable markings)

• Component C1 (Ain)
• Component C2 (R1)
• Component C3 (R2)
• Component C4 (R3)
• Component C5 (RY)
• Component C6 (Rout)

Low latency arbiter

Specification N

• Component C1 (A1,A2)
• Component C2 (R,G1,G2)

VME Bus Controller

Specification N (24 reachable markings) with structural auto-conflict

• Component C1 (dtack)
• Component C2 (lds,ds)

Locked2

Specification N (168 reachable markings) with dummy transition

• Removing dummy transition
• Component C1 (reqa)
• Component C2 (reqd)
• Component C3 (rdy)
• Component C3 (rdy) with risky strategy

Stg-Blunno

Specification N (1241 reachable markings) with dummy transition

(Source: a now obsolete webpage for the tool pipefitter of I. Blunno and L. Lavagno)

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