Current projects

• CAD Project
  
  
• High level language binding
  
  
• Technology mapping
  
  

The methode developed at the chair to synthesis asynchronous hasard tolerant sequential circuits, which each block from the circuits communicate with each other, is already implemented in the design-tool the so called CASCADE (Communicating Asynchronous Sequential Circuits: Architecture Development Environment). CASCADE possesses a graphical user-interface PED (Petri nets Editor) which is developed by Prof. Dr.-Ing. Monika Heiner (TU Cottbus) These PED have been adapted to CASCADE as a gSTG-Editor, which allowed one to specify gSTG special arcs like read arc and inhibitor arc.
CASCADE also includes converters to the well known tools like 3D (to the XBM-Synthese) and petrify. Already available, converter that make the transformation of the gSTGs into a XBM-Specification.(download STG2XBM). For more information about CASCADE, please see our publications or contact cascade@eit.uni-kl.de.

CASCADE with opened PED	Visualisation of the generated step-graph	CASCADE with opened data-file

What CASCADE still lacks of:

• Modules to gSTG decomposition and composition (to reduce complexity),
• an interface to hardware-description-languages (high-level-language-binding),
• Modules to the technology mapping,
• user friendly graphical interface.

We have many student and master thesis thema in this area to further development of CASCADE.

Existing synthese tools do not support technology mapping of the CASCACDE output. These existing tools do not keep the structure of the circuit specification, which is necessary for mapping asynchronous circuit. Therefore we develop new tool that mapping the circuit specification and still keep the structure such that no new hasard introduced.

Tool "techmap" in Test

Consulting partner: Dipl.-Ing. Karsten-Olaf Laux